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IPs Overview

ATHLET® is a family of IP cores for FPGA devices that address the need of embedded Graphic User Interface (GUI). Mainly, these IP cores have been designed to offer:
– Trade-off capability between features, performance and resources
– Easy integration
– Easy and fast applicative development

The ATHLET® IP is composed by a hardware part (the Video and Graphics Engine or VGE), and a software part (the driver) that allows customer application to handle the ATHLET® IP features through an Application Program Interface (API).
The typical system architecture is composed by a FPGA including the ATHLET® IP, a non-volatile memory including application program and data and a volatile memory that is used for program execution and GUI construction.
In ALTERA FPGAs, a Nios II CPU is instantiated into the device in order to run both the ATHLET® driver and the customer embedded application.
The volatile memory is shared between the application, the ATHLET® driver and the ATHLET® VGE. This unified memory architecture allows minimizing resources and system complexity and improves cost efficiency.

2 concepts, 2 cores for 2 needs

Mobile Object (MOBJ)

Management of Bitmap objects based on a legacy software API and patented hardware architecture.
Objects are said Mobile because their display parameters (alpha, position, size …) can be easily changed to reach dynamic and complex HMI. Software application runs on Nios II (Altera IP processor) and handles Mobile Objects through the Mobile Object API (ANSI C language).
These bitmap objects can be feed by different process:
– Still images (JPEG, PNG image files)
– True Type Font decoder
– Real-time Video
– Graphics (internal basic 2D renderer or external)
– SWF (ADOBE Flash content)

The unique benefits are:
– Capability to build attractive HMI at very small resources (see resources Table).
– Very short development time (hidden graphics complexity and intuitive object-oriented API).

SWF Player (ADOBE® Flash® content)

Very popular Flash authoring tools like Adobe Flash CS are often used for web design or Graphic User Interfaces prototyping.
Now, the Imagem SWF Player IP core allows you playing Flash content on a low-cost FPGA. Customer develops its Flash GUI on a desktop PC with standard Flash authoring tools (like Adobe Flash CS5) and then feed the IP core with the resulting SWF file (export format of the Flash content). The SWF Player IP core is then autonomous to display the GUI similarly to the PC Adobe Flash Player, offering a cross-platform GUI solution for embedded and industrial products.
Basically, the core is able to handle animations timelines and ActionScript (AS) codes execution. The IP core API allows system application to feed SWF GUI application with AS variables, keys events and cursor parameters in order to reach full interactivity.

ADOBE Flash inherent benefits are:
– Royalty-free (since May 2008).
– Standard and popular (wide community of developers & designers).
– Cost and time efficiency.
– Rich content, consumer-attractive GUI.

Imagem implementation benefits:
– World-first SWF Player IP core for low-cost FPGA.
– Cross-platform (designs your GUI on PC and runs it on the FPGA target, no conversion tools).
– High parallelism architecture for performance capability.
– Scalable IP core (customer tunable trade-off between resources & performance). 

ATHLET® IP Selection Matrix

 

ATHLET® Lite

ATHLET® Black

ATHLET® SWF

ATHLET® White

Cores

MOBJ

MOBJ

SWF

MOBJ+SWF

API, Library

Black

Black

SWF

Black & White

Description

Mobile Objects with
restricted features

Mobile Objects

SWF Player for 100%
ADOBE Flash GUI

Mobile Objects with
SWF content support

Typical resources

Final FPGA resources depends on IP configuration

LE -

~1700

3500~10000

10000~25000

13500~35000

M9K –

~7

11~22

18~60

29~82

DSP9x9 –

~6

6~40

35~100

41~410

Smaller FPGA device

(in
ALTERA Cyclone III)

EP3C5

EP3C10

EP3C25 (limited
features)

EP3C40 (full
features)

EP3C25 (limited
features)

EP3C40 (full
features)

Status

In Production

In Production

In Production

In Prototyping

Demonstration

-

Altera NEEK
(obsolete)

Terasic VEEK

-

Evaluation

-

-

Full

-

ATHLET® WHite Block Diagram

Full Overlay capability

Whatever the ATHLET® family, the IP core can be used as a Video & Graphics overlay generator with full alpha blending capability.
This overlay architecture guaranties the integrity of the main video both in term of latency (no latency because main video is not processed by the IP core) and data (blending equation can be implemented whatever the color dynamic of the main video), making this overlay architecture a relevant solution for applications where video integrity is very critical.

This overlay topology can be reached through a special configuration of the IP core. In this configuration:
– The ATHLET® display module self-synchronizes on the main video timings.
– The ATHLET® display port output per-pixel transparency (8 bits alpha) information.
– The ATHLET® overlay image has transparent background color (alpha=0).

Outside the ATHLET® IP, it becomes possible to merge the overlay image with the main video image by implementing the following equation:

This equation implements the standard SRC_OVER compositing operator assuming the overlay Image is over the main image. In this overlay configuration, ATHLET® R,G,B output channels are already multiplied with alpha channel.