• A modular solution for Video, graphics and Display into Intel FPGAs.
  • A coherent Video and Image Processing (VIP) Suite of IP cores for the processing of live videos, raster and vector images, and for the production of display HMIs.

The accelerations need for Video, Graphics and Display

A modern architecture for display HMI involves a distributed acceleration with several hardware accelerators aiming at offloading the main processor unit.

ATHLET VIP provides a set of IP cores answering the accelerations needs, as described into the following table.

IP cores overview

The following table details the included IP cores and their main features.

ATHLET IP name Acceleration Description / Main features
Multi-Layers, Display Controller Patented architecture
Screen composition of multiple layers (=Overlay)
Huge number of layers can be composed on-the-fly.
Many layers properties (position, size, windowing, clipping, transparency, masking, color-keying, color-transforms…).
– Layers tightly coupled to ATHLET Surfaces for displaying of still images, animations, live-video or graphics rendered content.Native support for multi-screens (same timings & resolution).
– Native support for screen-buffer and Screen layout with horizontal/vertical flip and 0/90/180/270° rotation.
– Versatile video output (streamed, clocked, timing controller).
– High configurability for user trade-off between high performance/small resources/full-features.
– Multi-instantiable IP core for multi-displays applications.
Vector-Graphics Renderer
2D graphics acceleration for Vector-Graphics including:
Bezier Paths Rasterization:
– High-quality antialiasing (256 gray levels).
– Very limited memory consumption.
– Painting with linear/radial gradients and spread options.
– Affine transformations for path and paint.
– Utilities for paths generation (rectangles, ellipses, polygons, stars, …).
– Utilities for matrices generation.
Images Composition:
– Clearing, copy, composition
Images Transformation:
– 2D-affine transformation (3×2 matrix).
– Bilinear interpolation.
Rich pipeline options:
– clipping, masking, color-transform, blending…
Multi-pixels in parallel for user-configuration between low-resources/high-performance.
High configurability for user trade-off between high performance/small resources/full-features.
Raster Images based on ATHLET Surfaces for easy share with other VIP accelerators.
Video Surface Converter
Conversion in-between real-time video stream and memory Surface.
Versatile core topology supporting:
1- Surface Writer which performs Video-to-Surface conversion.
2- Surface Reader which performs Surface-to-Video conversion.
3- Surface Buffer which performs Video-to-Surface-to-Video double conversion.
Included basic image transformation:
– Translation
– Rotation (0, 90°, 180°, 270°)
Video streams interface compliant to Avalon-ST Video.
Memory Surfaces compliant to ATHLET Surfaces.
Multi-pixels in parallel for throughput user-configuration.
Multi-instantiable IP core for several video conversions in parallel.

These IP cores use a common concept and specification for 2D raster images, called ATHLET Surface, to easily share still images, graphics rendered or live video indifferently.

A complementary with Intel FPGA VIP

ATHLET VIP provides concept and specification for memory surfaces through ATHLET Surface.

Intel FPGA VIP provides concept and specification for video streams through Avalon-ST Video protocol.

The ATHLET VIP provides a coherent set of IP cores which fully satisfy the Display HMI needs.

For each video input of the ATHLET subsystem, the Intel VIP may be used to perform a pre-processing of the video stream.
For each display output of the ATHLET subsystem, the Intel VIP may be used to perform a post-processing of the video stream.

Product Overview

IP cores features:

  • Encrypted VHDL netlist
  • Intel FPGA Qsys compliant (integration in minutes)
  • High configurability (small ressource, high performance, full-features…)
  • Hardware Abstraction Layer (HAL) and utilities in ANSI C.
  • System Console Dashboard (runtime control, debug and monitoring)
  • Full documentation

Delivery Package

  • IP cores
  • Getting Started
  • Reference designs
  • Opencores Plus license

Business Model

  • For FREE evaluation (full-features, OpenCores Plus)
  • Low Volume or Standard Licensing Model
  • Basic or Premium support


Latest Release

Version Release date Download
1.2 2018/01*

(*) This package can be downloaded for free after filling the evaluation form by clicking here.

Licensing Model

Two licensing models co-exist to provide the right answer to the right need.

  • Low-Volume Licensing Model for projects with low-volumes. This model provides both the most affordable IP cost and the most simplified purchasing process using the Imagem online shop.
  • Standard Licensing Model for any other cases. Contact Imagem to get a quote.
  Low-Volume Licensing Model Standard Licensing Model
Number of manufactured units 5000 units maximum No limit
License Type Time-Based Permanent
License Duration 1, 2 or 3 years unlimited
License Contract Online (Click form) Paper form
License Fee UpfrontOnline shop Upfront or royalties
Developer seats limitation 1 (seat or float) No limit at the specified geographic location
Included Support Basic support Basic support
Additional support Premium support on demand Premium support on demand
Payment Credit Cards, PayPal … As agreed

Low-Volume Licensing Model Pricing

Product Ordering code License Price (EUR)
ATHLET VIP ATH_VIP_LV1* 1 year 5000
ATH_VIP_LV2* 2 years 8000
ATH_VIP_LV3* 3 years 9500
Additional seat (fixed or float) 1000

(*) includes:
– 1 float license (server NIC-ID) or 1 node-locked license for 2 computers (2 NIC-ID)
– MAX10 + 1 customer-defined FPGA device family

Getting Started

To get started with the ATHLET VIP, Imagem Technology provides with comprehensive and ready-to-use reference designs.

The chosen reference platform is the MAX10 NEEK (or just NEEK10) provided by Terasic.

This platform features a MAX10 50KLE, 2 video inputs (HDMI-Rx, Camera), Multi-touch 800×480 TFT LCD…

The combination of the NiosII ecosystem with the ATHLET IPs Suite makes it possible to implement a complete System-On-Chip for display HMI within a MAX10 FPGA device.

The built-in reference designs allow indistinctly:

  • Running the built-in ATHLET demos with NEEK10 application selector (demos available for download here).
  • Software evaluation using built-in hardware design.
  • Hardware evaluation using ATHLET VIP full package.

The reference designs and the Getting Started documentation are included into the ATHLET VIP package. This package can be downloaded after filling the evaluation form by clicking here.